1. Field of the Invention
The present invention relates to techniques for transmitting data through electrical signals. More specifically, the present invention relates to a method and an apparatus that latches a dataword after detecting a predetermined number of signal line transitions, wherein each transition between successive datawords involves a minimum number of transitions on a set of signal lines.
2. Related Art
As processor clock speeds continue to increase at an exponential rate, data must be transferred at correspondingly faster rates between computer system components. Computer systems typically use large parallel busses for this purpose.
These large parallel busses typically use either single-ended signaling or differential signaling. Single-ended signaling makes use of a single signal line to carry each bit, along with one or more clock lines to latch the signals.
In contrast, differential signaling uses two signal lines to carry each bit, wherein the value of the bit is indicated by a voltage difference between the two signal lines. Because currents are balanced between power and ground rails, differential signaling reduces power supply noise and solves the problem of where return currents come from. Moreover, differential signaling is less sensitive to ground shifts between sender and receiver because differential signaling relies on voltage differences between pairs of signal lines, instead of relying on an absolute voltage level of a single signal line.
Unfortunately, differential signaling uses twice as many wires as single-ended signaling, which can greatly exacerbate pin limitation problems.
What is needed is a method and apparatus for transferring data between computer system components without the large number of signal lines required by differential signaling, and without the current balance and ground noise problems of single-ended signaling.
Another problem that has to be dealt with in transferring data across a parallel bus is to efficiently latch the data signals when they are received at a receiver. Many systems include one or more additional clock lines in the parallel bus to carry a clock signal, which is used to latch data at a receiver. These additional clock lines increase the number of signal lines required to transfer the data. Moreover, there is typically a significant amount of xe2x80x9cskewxe2x80x9d between the clock signal and the rest of the data lines. This means that a latching operation triggered by the clock signal typically has to be delayed to accommodate the worst-case possible skew between the clock signal and the data lines.
Hence, what is needed is a method and an apparatus for latching data from a parallel bus without the above-described problems.
One embodiment of the present invention provides a system that keeps track of transitions on signal lines in order to latch a dataword in a stream of datawords. This stream of datawords is generated so that each transition between successive datawords involves a minimum number of transitions on a set of signal lines. During operation, the system monitors the set of signal lines that carries the stream of datawords. Upon detecting a predetermined number of transitions on the set of signal lines, the system waits a fixed time interval to ensure that a dataword is ready to be latched, and then latches the dataword.
In a variation on this embodiment, each transition between datawords involves a substantially equal number of rising and falling transitions. In a further variation, each dataword in the stream of datawords has a substantially equal number of ones and zeros.
In a variation on this embodiment, detecting the predetermined number of transitions involves using separate circuits to detect a predetermined number of rising transitions and a predetermined number of falling transitions. Furthermore, latching the dataword involves using separate circuits to latch signal lines involved in rising transitions and signal lines involved in falling transitions.
In a variation on this embodiment, the fixed time interval includes latch setup time. In a further variation, the fixed time interval accounts for the maximum possible skew between when the predetermined number of transitions occurs and when all signals lines for the dataword are valid.
In a variation on this embodiment, the predetermined number of transitions can include any number of transitions, from a single transition to the minimum number of transitions between successive datawords.
In a variation on this embodiment, the predetermined number of transitions is substantially half the minimum number of transitions between successive datawords.
In a variation on this embodiment, detecting the predetermined number of transitions involves performing current summing.
In a variation on this embodiment, the system performs input amplification on the set of signal lines, wherein the input amplification involves performing a voltage averaging operation over the set of signal lines to determine a reference voltage. This voltage averaging can be accomplished by using a current summing circuit.